The escalating demands for high density and performance associated with ultra large scale integration semiconductor devices require very small design features, high reliability and increased manufacturing throughput. The reduction of design features challenges the limitations of conventional methodology.
For example, there are a number of problems associated with attempting to form narrow device features in a conductive material, such as silicon or polycrystalline silicon. More particularly, the desired width of the device features are often much smaller than that which can be directly formed using lithography.
Spacers are often used as etch masks to attempt to form the desired device features. Spacers, however, are inherently asymmetrical and present problems during etching. For example, hard mask erosion associated with spacers adversely affects the final feature profile. Such problems often result in an undesirable feature profile that may lead to device performance problems and/or reliability problems.